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april 2009 rev 2 1/33 33 l6585de combo ic for pfc and ballast control features pfc section ? transition mode pfc with over-current protection ? over-voltage protection ? feedback disconnection ? under-voltage lockout ? pfc choke saturation detection ? thd optimizer half-bridge section ? preheating and ignition phases independently programmable ? 3 % oscillator precision ? 1.2 s dead time ? programmable and precise end-of-life protection compliant with all ballast configurations ? smart hard swit ching detection ? fast ignition voltage control with choke saturation detection ? half-bridge over-current control so-20 figure 1. block diagram www.st.com
contents l6585de 2/33 contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 vcc section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 pfc section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.1 tm pfc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.2 leading edge blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.3 thd optimizer feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.4 over-voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.5 disabling the l6585de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.6 feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.7 pfc over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 ballast section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 half-bridge drivers and integrated bootstrap diode . . . . . . . . . . . . . . . . . 18 6.2 normal start-up description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 startup sequence with old or damaged lamps . . . . . . . . . . . . . . . . . . . . . 21 6.4 old lamp management during run mode . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 rectifying effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.7 hard switching protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
l6585de contents 3/33 6.8 choke saturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
pin settings l6585de 4/33 1 pin settings 1.1 connection figure 2. pin connection (top view) 1.2 functions table 1. pin functions pin n. name function 1osc an external capacitor to ground fixes the half-bridge switching frequency with a 3 % precision. 2rf voltage reference capable of sourcing up to 240 a. the current sunk from this pin fixes the switching frequency of the half-bridge for each operating state. a resistor ( r run ) connected to ground sets the half-bridge operating frequency combined with the capacitor connected to the pin osc. a resistor connected to eoi (r pre ) sets the maximum half-bridge switching frequency during preheating combined with r run and c osc . 3eoi connected to ground by a capacitor that, combined with r pre , determines the ignition time. preheating : low impedance to set high switching frequency ignition and run mode : high impedance with controlled current sink in case of hbcs threshold triggering.
l6585de pin settings 5/33 pin n. name function 4tch pin for setting the preheating time and protection intervention. connect an rc parallel network (r d and c d ) to ground. preheating : the c d is charged by an internal current generator. when the pin voltage reaches 4.63 v the generator is disabled and the capacitor discharges because of r d . once the voltage drops below 1.5 v, the preheating finishes, the ignition phase starts and the r d c d is pulled to ground. ignition and run mode: during proper behavior of the ic, this pin is low impedance. during a fault (either over-current or eol) the internal generator charges the c d to 4.63 v and then another current generator discharges the same capacitor. in this way, c d sets the fault timing (shorter than preheating time). 5eolp pin to program the eol comparator. it is possible to select both the eol sensing method (fixed reference or reference in tracking with ctr) and the window comparator amplitude by connecting a resistor (r eolp ) to ground. 6eol input for the window comparator. it can be used to detect lamp ageing for either ?lamp to ground? or ?block capacitor to ground? configurations. this function is blanked during the ignition phase. 7ctr input pin for: - pfc over-voltage detection: the pfc driv er is stopped until the voltage returns in the proper operating range - feedback disconnection detection - reference for eol comparator (in case tracking reference) - the pin can be used also for shutdown 8mult multiplier external input. this pin is connected to the rectified mains voltage via a voltage divider and provides the sinusoidal reference to the pfc current loop. 9comp output of the error amplifier. a compen sation network is placed between this pin and inv to achieve stability of the pfc voltage control loop and ensure high power factor and low thd. 10 inv inverting input of the error amplifier. ou tput voltage of the pfc pre-regulator is fed to the pin through a voltage divider. 11 zcd boost inductor demagnetization sens ing input for pfc transition-mode operation. a negative-going edge triggers pfc mosfet turn-on. during startup or when the voltage is not high enough to arm the internal comparator, the pfc driver is triggered by means of an internal starter. 12 pfccs input to the pfc pwm comparator. the current flowing through the pfc mosfet is sensed through a resistor. the re sulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine the pfc mosfet? s turnoff. a second comparison level detects abnormal currents (due to boost inductor saturation, for example) and, on this occurrence, shuts down the pfc gate. an internal leb prevents undesired function triggering. table 1. pin functions (continued)
pin settings l6585de 6/33 pin n. name function 13 pfg pfc gate driver output. t he totem pole output stage is able to drive power mosfets with a peak current of 300 ma source and 600 ma sink (typ. values). 14 hbcs 3-level half-bridge current monitor for cu rrent control. the current flowing through the hb mosf et is sensed through a resistor. the resulting voltage is applied to this pin. first level threshold (1.05 v, active during run mode): in case of threshold crossing the ic reacts with frequency increase in order to limit the half-bridge (and lamp) current. second level threshold (1.6 v, active during ignition and run mode): - ignition : in case of threshold crossing during the frequency shift, the ic reacts with frequency increase in order to limit the lamp voltage and preventing operation below resonance. - run mode : in case of threshold crossing because of current spikes (due, for example, to capacitive mode / cross-conduction) longer than 200 ns the l6585de is latched in low consumption mode to avoid damage to the mosfets. third level threshold (2.75 v, active during ignition and run mode): - ignition : in case of threshold crossing during frequency shift (e.g. caused by choke saturation), the ic latches to avoid damage to the mosfets. - run mode : in case of threshold crossing by a hard switching event (spike duration equal to around 40 ns) an internal counter is increased. after around 350 (typ.) subsequent hard switching event s the ic is latched in low consumption mode. 15 gnd ground. 16 lsd low side driver output: the output stage can deliver 290 ma source and 480 ma sink (typ. values). 17 vcc supply voltage of both the signal part of the ic and the gate driver. clamped with a zener inside. 18 out high-side driver floating reference. this pin must be connected close to the source of the high side power mosfet. 19 hsd high-side driver output: th e output stage can deliver 290 ma source and 480 ma sink (typ. values). 20 boot bootstrapped supply voltage. bootstra p capacitor must be connected between this pin and out pin. patented, integrated circuitry replaces the external bootstrap diode by means of a high voltage dmos, synchronously driven with the low side power mosfet. table 1. pin functions (continued)
l6585de electrical data 7/33 2 electrical data 2.1 maximum ratings note: esd immunity for pins 18, 19 and 20 is guaranteed up to 900 v (human body model) 2.2 thermal data table 2. absolute maximum ratings symbol pin parameter value unit v boot 20 floating supply voltage -1 to 618 v v out 18 floating ground voltage -3 to v boot ? 18 v dv out /dt 18 floating ground max. slew rate 50 v/ns v cc 17 ic supply voltage (i cc = 20 ma) (1) 1. the device has an internal clamping zener between g nd and the vcc pin. it must not be supplied by a low impedance voltage source. self-limited v 1, 3, 4, 8, 10, 12 analog input and outputs -0.3 to 5 v 2, 5 -0.3 to 2.7 v v eol 6 maximum eol voltage -0.3 to v cc v v ctr 7 maximum ctr voltage -0.3 to 7 v v hbcs 14 maximum half-bridge current sense voltage -5 to 5 v 9, 11 self-limited i rf 2 current capability 240 a i eolp 5 current capability 100 a f osc(max) maximum operating frequency 250 khz p tot power dissipation @t a = 70 c 0.83 w table 3. thermal data symbol description value unit r thja max. thermal resistance junction to ambient 120 c/w t j junction operating temperature range -40 to 150 c t stg storage temperature -55 to 150 c
electrical characteristics l6585de 8/33 3 electrical characteristics v cc = 15 v, t a = 25 c, c l = 1 nf, c osc = 470 pf, r run = 47 k , unless otherwise specified table 4. electrical characteristics symbol pin parameter test condition min. typ. max. unit supply voltage vcc v cc operating range after turn-on 11 16 v v cc(on) v cc turn-on threshold (1) 13.6 14.3 15 v v cc(off) v cc turn-off threshold (1) 9.6 10.3 11 v v z v cc zener voltage icc = 20 ma, t a = 25 c 16.7 17.1 17.5 v icc = 20 ma, full temperature range 16 17.1 18 v supply current i st-up v cc start-up current before turn-on @ 13 v 250 370 a i cc v cc operating supply current fpfc = 50 khz 7 ma iq v cc residual current ic latched 350 a pfc section ? multiplier input i mult mult input bias current v mult = 0 v -1 a v mult mult linear operation range v comp = 3 v 0 to 3 v v cs v mult mult output max. slope v mult = 0 to 1 v, v comp = upper clamp 0.75 v/v k m mult gain v mult = 1 v, v comp = 3 v 0.52 1/v pfc section ? error amplifier v inv inv voltage feedback input threshold 2.47 2.52 2.57 v inv line regulation v cc = 10.3 v to 16 v 50 mv i inv inv input bias current -1 a gv inv voltage gain open loop (2) 60 80 db gb inv gain-bandwidth product (2) 1mhz i comp comp source current v comp = 4v, v inv = 2.4 v -2.6 ma sink current v comp = 4v, v inv = 2.6 v 4 ma v comp comp upper clamp voltage i source = 0.5 ma 4.2 v lower clamp voltage i sink = 0.5 ma 2.25 v v dis inv open loop detection threshold ctr > 3.4 v 1.2 v comp static ovp threshold 2.1 2.25 2.4 v
l6585de electrical characteristics 9/33 symbol pin parameter test condition min. typ. max. unit ctr pin dis ctr shutdown threshold falling edge 0.75 v hysteresis 120 mv pfov ctr dynamic pfc over- voltage rising edge 3.4 v hysteresis 140 mv ctr available range as tracking reference lower threshold (falling) 1.7 v hysteresis 120 mv higher threshold (rising) 3.4 v hysteresis 140 mv pfc section ? current sense comparator i cs pfcs input bias current v cs = 0 v -1 a t leb pfcs leading edge blanking (2) 100 200 300 ns v csstop pfcs pfc stop threshold v ctr 1.65 1.75 1.85 v t d(h-l) pfcs delay to output 120 ns v csclamp pfcs current sense reference clamp v comp = upper clamp 1 1.08 1.16 v pfc section ? zero current detector v zcdh zcd upper clamp voltage i zcd = 2.5 ma 5 v v zcdl zcd lower clamp voltage i zcd = -2.5 ma -0.3 0 0.3 v v zcda zcd arming voltage (positive-going edge) (2) 1.4 v v zcdt zcd triggering voltage (negative-going edge) (2) 0.7 v i zcdb zcd input bias current v zcd = 1 to 4.5 v 1 a i zcdsrc zcd source current capability -4 ma i zcdsnk zcd sink current capability 4 ma pfc section ? gate driver pfg output high/low i sink = 10 ma 0.2 v i source = 10 ma 14.5 v tf pfg fall time 40 90 ns tr pfg rise time 90 140 ns i sink pfg peak sink current 475 600 ma i source pfg peak source current 200 300 ma pfg pull-down resistor 10 k table 4. electrical characteristics (continued)
electrical characteristics l6585de 10/33 symbol pin parameter test condition min. typ. max. unit half bridge section ? timing and oscillator i ch t ch charge current v tch = 2.2 v 31 a v chp t ch charge threshold (positive going-edge) (1) 4.53 4.63 4.73 v v chn t ch discharge threshold (negative going edge) (1) 1.50 v t ch leakage current 1.5 v < v tch < 4.5 v, falling 0.1 a i chsnk t ch discharge current during protection: reduced timing v tch = 3 v 26 a r tch t ch internal impedance run mode 100 200 eoi open state current v eoi = 2 v 0.15 a r eoi eoi eoi impedance during preheating 150 i eoi eoi eoi current generator during ignition and run mode tspike = 200 ns (3) 20 a tspike = 400 ns (3) 100 tspike = 600 ns (3) 200 tspike = 1 s (3) 270 v eoi eoi eoi threshold (1) 1.83 1.9 1.98 v v ref rf reference voltage (1) 1.92 2 2.08 v i rf rf max current capability 240 a i oscratio osc i osc /i rf v osc = 3 v 4 osc rising threshold (1) 3.7 v osc falling threshold (1) 0.9 v d osc output duty cycle 48 50 52 % t dead osc dead time 0.96 1.2 1.44 s f run osc half-bridge oscillation frequency (run mode) 58.4 60.2 62 khz f pre osc half-bridge oscillation frequency (preheating) r pre = 50 k 113.2 116.7 120.2 khz half bridge section ? end-of-life function i eolp eolp current capability 100 a v eolp eolp reference voltage 1.92 2 2.08 v eol operating range eolp = 27 k 0.95 4.15 v v s eol window comparator reference 220 k < r eolp < 270 k or 22 k < r eolp < 27 k tracking with ctr v r eolp > 620k or 75 k < r eolp < 91 k 2.5 table 4. electrical characteristics (continued)
l6585de electrical characteristics 11/33 symbol pin parameter test condition min. typ. max. unit v w eol half window amplitude 220 k < r eolp < 270 k +250 mv -240 22 k < r eolp < 27 k +160 -150 r eolp > 620 k 720 75 k < r eolp < 91 k 240 eol sink/source capability 5.5 a half bridge section ? half-bridge current sense hbcs h hbcs frequency increase v eoi < 1.9 v ( ignition ) 1.53 1.6 1.66 v hbcs l hbcs threshold v eoi > 1.9 v ( run mode ) 0.98 1.05 1.12 v hbcs h,test hbcs shut down threshold during first low side on time after tch cycle v eoi < 1.9 v ( ignition ) 1.05 v hbcs l,test hbcs v eoi > 1.9 v ( run mode )0.82 v hbcs as hbcs anti saturation threshold ignition 2.75 v t leb,hbcs hbcs leading edge blanking ignition 270 ns hbcs cm hbcs capacitive mode threshold run mode, tpulse > 200 ns 1.53 1.6 1.66 v hbcs hs hbcs hard switching detector run mode, tpulse > 40 ns 2.75 v hysteresis 450 mv n hs hard switching events before shutdown run mode 350 half bridge section ? low side gate driver lsd output low voltage i sink = 10 ma 0.3 v lsd output high voltage i source = 10 ma 14.5 v lsd peak source current 200 290 ma lsd peak sink current 400 480 ma t rise lsd rise time 120 ns t fall lsd fall time 80 ns lsd pull-down resistor 45 k half bridge section ? high side gate driver (voltages referred to out) hsd output low voltage i sink = 10 ma v out + 0.3 v hsd output high voltage i source = 10 ma v boot ? 0.5 v hsd peak source current 200 290 ma hsd peak sink current 400 480 ma table 4. electrical characteristics (continued)
electrical characteristics l6585de 12/33 symbol pin parameter test condition min. typ. max. unit t rise hsd rise time 120 ns t fall hsd fall time 80 ns hsd hsd-out pull-down 50 k high-side floating gate-drive supply boot leakage current v boot = 600 v (2) 5a out leakage current v out = 600 v (2) 5a synchronous bootstrap diode on-resistance v lsd = high 250 1. parameter in tracking 2. specification over the -40 c to 125 c junction temperature range are ensured by design, characteriza tion and statistical correlation 3. a pulse train has been sent to the hbcs pin with f = 6 khz; the pulse duration is the one indicated in the notes as "ton" table 4. electrical characteristics (continued)
l6585de device description 13/33 4 device description the l6585de embeds a high performance pfc controller, a ballast controller and all the relevant drivers necessary to build an electronic ballast. the pfc section achieves current mode control operating in transition mode, offering a highly linear multiplier including a thd optimizer that allows for an extremely low thd, even over a large range of input voltages and loading conditions. the pfc output voltage is controlled by means of a voltage-mode error amplifier and a precise internal voltage reference. the ballast controller offers t he designer a very precise oscilla tor, a logic that manages all the operating steps and a full set of protection features: programmable end-of-life detection, compliant with both lamp-to-ground and capacitor- to-ground configurations over-current protection with either current limiting or choke saturation protection hard switching events detection high current capability drivers fo r both the pfc (300 ma sour ce and 600 ma sink) and the half-bridge (290 ma source and 480 ma sink) also allow ballast designs for very high output power (up to 160 w).
application information l6585de 14/33 5 application information figure 3. typical application 5.1 vcc section the l6585de is supplied by applying voltage between the v cc pin and gnd pin. an under- voltage lockout (uvlo) prevents the ic from operating with supply voltages too low to guarantee the correct behavior of the internal structures. an internal voltage clamp limits the voltage to around 17 v and can deliver up to 20 ma. for this reason it cannot be used directly as a clamp for the charge pump (current peaks usually reach several hundreds of ma), but can be easily used during startup in order to charge the v cc capacitor or during save mode in order to keep the ic alive, for example, connecting v cc to input voltage through a resistor. in addition to the bulk capacitor (>1 f)it is suggested to place a 100 nf ceramic capacitor close to v cc pin.
l6585de application information 15/33 5.2 pfc section 5.2.1 tm pfc operation the pfc stage contains all the features needed to implement a transition mode pfc controller. figure 4. pfc section the control loop can be implemented thanks to the high performance error amplifier and the very precise internal voltage reference that fixes the non-inverting input of the e/a to 2.52 v 2 %. the control loop reacts in order to bring the inverting input to the same voltage. connecting the high voltage rail to inv pin, by means of a voltage divider, t he output voltage will be easily set. the output of the e/a can be used in order to compensate the control loop with an rc network or, more often, with a simple capacitor connected between inv and comp pin. the output voltage of the e/a is also fed to t he multiplier. this block multiplies the waveform present at the mult pin by the output of the e/a. the resulting volt age will be used as the threshold for the current sense input. an internal clamp limits the threshold to a maximum value equal to 1 v. in figure 5 the characteristic curves of the multiplier are reported. figure 5. multiplier
application information l6585de 16/33 the zcd input can be co nnected directly to an auxiliary winding of the pfc choke in order to turn on the mosfet when the choke current reaches zero. this pin has internal clamps and high current capability that makes it compliant with a very wide range of input voltage. at startup, when pfc choke is not yet energized, an internal starter gives zcd pulses to the pfc gate driver with a repetition rate of approximately 15 khz. by turning off the mosfet when the current reaches the threshold and turning on the mosfet when the choke current reaches zero, a triangular input current whose peaks are modulated by the mult voltage is obtained. by feeding the mult pin with the mains waveform, a power factor correction and thd reduction is achieved. 5.2.2 leading edge blanking usually current sense voltage is filtered by means of an rc network in order to avoid false turning off of the mosfet because of the discharge current related to parasitic drain capacitance present at the beginning of the on time of the mosfet. this filtering generates a delay between the actual threshold crossing and the input triggering. during this time the pfc inductor current increases and the choke may saturate. a leading edge blanking structure makes the pfccs input active only after 200 ns (typ.) after the pfg turn on. this allows the use of inductors with lower saturation current. however, if saturation occurs, a choke saturation protection turns off the pfc gate as soon as the voltage at pin pfccs is above 1.7 v. figure 6. pfccs waveforms 5.2.3 thd optimizer feature when the input voltage passes through zero, the pfc choke cannot store energy because of the very low voltage across it. this may cause heavy crossover distortion and subsequent thd degradation. a small offset voltage superimposed over the mult voltage can reduce this issue. the internal thd optimizer increases the performance when the mains voltage reaches zero; this reduces crossover distortion and avoids offset introduction.
l6585de application information 17/33 5.2.4 over-voltage protection two different over-voltage protections can be detected: dynamic over-voltage, usually due to fast load transition and static over-voltage, due to an excessive input voltage. dynamic ovp the ctr pin is connected to high voltage rail through a voltage divider. if the voltage at this pin is above 3.4 v, the pfc gate driver is stopped until the voltage returns below the threshold. this limits the risk of choke saturation and mosfet's damage. static ovp a steady over-voltage may cause abnormal behavior in both the pfc (e.g. because input voltage is higher than pfc output voltage) and the ballast (e.g. overheating, lamp over-current, capacitive mode operating poin t). a steady over-voltage causes a slow transition of the comp pin towards the low saturation (around 2.25 v). this fact is considered by the l6585de as a static over-voltage event and a tch cycle is started. after this cycle, if the comp pin is saturate d low the ic is latched in low consumption mode. 5.2.5 disabling the l6585de the ctr pin can be used to shut down the ic without mains disconnection. when ctr is pulled below 0.75 v, the ic is stopped and the internal logic is reset. when ctr is released, the ic starts with a new preheating sequence. this function is available only if the ic is not latched due to a fault protection intervention. 5.2.6 feedback disconnection protection very fast output voltage surges may damage the upper resistors of the voltage divider feeding the inv pin, causing a feedback disconnection. in this case, the e/a saturates high and the pfc gate drive turns on the mosfet for a long time (the current sense threshold assumes its maximum value equal to 1 v) and the choke may saturate, destroying the mosfet. the output voltage increases very fast and may reach very high value even if ovp is triggered. feedback disconnection protection is then activated if v inv < 1.2 v and dynamic over- voltage protection is triggered. 5.2.7 pfc over-current protection the pfc mosfet over-current can occur in cases of pfc choke saturation or in cases of surge from the input, due to the breakdown of the mosfet body diode. the latter case is observed together with an over-voltage of the pfc output. in both cases, the pfc stage is stopped, whereas the hb stage continues switching. the protection is not latched: once the pfccs falls below 1.7 v, the pfc driver restarts.
ballast section l6585de 18/33 6 ballast section 6.1 half-bridge drivers and integrated bootstrap diode the half-bridge drivers are capable of 290 ma source and 480 ma sink current. this makes them able to effectively drive also big mosfets cg up to 2.2 nf. the high-side mosfet is driven by means of a bootstrapped structure reducing the number of external components. 6.2 normal start-up description referring to figure 7 , normal startup proceeds as follows: figure 7. normal start-up procedure 1. startup : as soon as vcc reaches the startup threshold voltage references are built up, the rf and eolp pin are biased, the eoi pin is pulled down and the tch pin starts sourcing 31 a. the frequency of the half-b ridge is generated by an internal cco, connected to c osc and using the rf current as the control signal. with the eoi pin pulled down, the startup freq uency will be due to the current flowin g in parallel with r pre and r run (see typical application diagram). 2. preheating: the tch pin continues to source 31 a until its voltage reaches 4.63 v, therefore it is left in a high impedance status. as this pin loaded with an rc parallel network, the voltage across this pin decreases exponentially. when it reaches 1.5 v the tch pin is pulled down and the preheating time ends. during this sequence the eoi pin is pulled down and the half-bridge frequency is the startup frequency. a leading
l6585de ballast section 19/33 edge blanking is active during this time in order to avoid any detection of hard switching events, very common during this phase. 3. ignition: at the end of the tch cycle, the eoi pin is left free in high impedance mode. therefore, the capacitor connected between eoi and ground is charged by rf through r pre . the current sunk from the rf pin decreases exponentially, and the frequency along with it. an exponential decrease in switching frequency causes a linear increase of the lamp voltage. when the lamp voltage reaches the strike value, the lamp ignites. ignition time is set by the value of r pre and c ign . during ignition current control protection, anti-ballast choke saturation protection and leading edge blanking are all active. figure 8. half-bridge protection thresholds during ignition 4. run mode: when the eoi voltage reaches 1.9 v, the ic enters run mode and the switching frequency is set only by r run . current control protection and anti-ballast choke saturation are now active with a lower threshold, leading edge blanking is not active and a fast hard switching detector is activated. figure 9. half-bridge protection thresholds during run mode
ballast section l6585de 20/33 the oscillator characteristic curves repr esent the half bridge frequency versus the resistance r placed between rf pin and ground. during preheating r is equal to r run in parallel with r pre whereas during run mode r is equal to r run . each curve is related to a value of the c osc capacitor and are depicted in figure 10. the value of c osc is measured between pin 1 (osc) and 15 (gnd); for other capacitor values please refer to an2870. the right value of r during preheating and run mode can be found graphically considering the curve related with the chosen capacitor and respectively f pre and f run ? figure 10. oscillator characteristics some useful equations are given: ign pre ign d d d ch tch pre c r 3 t 5 . 1 63 . 4 ln c r c i 63 . 4 t t ? ? ? ? ? ? ? ? ? ? + = =
l6585de ballast section 21/33 6.3 startup sequence with old or damaged lamps when an old lamp is connected to the ballast the strike voltage is higher than the nominal voltage and may also be higher than the safety threshold. in this case the lamp can ignite in a time longer than ignition time or may not ig nite. in both cases, during ignition time, because of the frequency decrease, the voltage at the output of the ballast can easily reach dangerous values. the same occurs if the lamp tube is broken: the lamp cannot ignite and the lamp voltage must be limited. during ignition time, the l6585de senses the cu rrent flowing into the lamp through a sense resistor connected to the hbcs pin. if the hbcs pin voltage reaches 1.6 v, a small amount of current is sunk from the eoi pin causing a small frequency increase. this frequency modification results, macrosco pically, in a frequency regula tion and therefore a current regulation and a lamp voltage limiting. as soon as the hbcs pin voltage reaches 1.6 v, the tch pin starts to charge cd: when the tch voltage reaches 4.63 v, the tch pin is no longer left free (as during preheating), but it sinks 26 ua, causing a faster discharge of cd. when the tch voltage reaches 1.5 v, the pin is pulled down and hbcs voltage is checked. if it is above 1.05 v the ic is stopped. if the lamp ignites during this reduced tch cycle , the eoi pin stops sinking current and if it reaches 1.9 v, the ic enters run mode and tch pin is immediately pulled down. figure 11. startup procedures with old or damaged lamps it can be noted that the reduced tch cycle time depends only on the value of cd. it is suggested to start from the choice of cd in order to obtain the protection time, and then can proceed to the choice of rd to obtain the desired t pre . 6 d snk , tch source , tch d reduced , tch 10 26974 . 0 c i 5 . 1 63 . 4 i 63 . 4 c t ? ? ? ? ? ? ? ? ? ? ? ? + =
ballast section l6585de 22/33 6.4 old lamp management during run mode during run mode, an old lamp can exhibit three different abnormal behaviors: rectifying effect over-current hard switching event 6.5 rectifying effect the rectifying effect is related to a differentia l increase of the ohmic resistance of the two cathodes. the lamp equivalent resistance is therefore higher when the lamp current flows in one direction than in the other. the current waveform is distorted and the mean value of the lamp current is no longer zero. the eol pin is the input of an internal window comparator that can be triggered by a voltage variation due to rectifying effect. the reference of this comparator and the amplitude of the window can be set by connecting a suitable resistor to eolp pin as indicated in following table: the reference of this comparator can be set at a fixed voltage or at the same voltage as the ctr pin. the fixed reference configuration (see figure 12 ) can be used when the lamp is connected to ground, and requires two zener diodes in order to shift the mean value of the lamp voltage to 2.5 v. the values of the two zeners affect the symmetry of the intervention of the protection: the best symmetry is obtained choosing two values whose difference is equal to twice the reference voltage: v up = v ref + v z2 + v f1 + w/2 v down = v ref ? (v z1 + v f2 ) ? w/2 v up = - v down 2 v ref = v z1 ? v z2 where v up and v down are the maximum allowed values of v k the tracking configuration (see figure 13 ) is useful when the la mp is connected between choke and blocking capacitor in the block ca pacitor-to-ground configuration. in this configuration the voltage across the blocking capacitor is affected by the voltage ripple superimposed on the pfc output. using a reference affected by the same ripple helps to reject it and avoid premature triggering of the comparator. as soon as the comparator is triggered, a tch cycle starts in order to improve the noise immunity. table 5. eol window comparator configuration table eolp resistor range reference window amplitude (wv) 22 k 27 k v ctr +160 mv / -150 mv 75 k 91 k 2.5 v 240 mv 220 k 270 k v ctr + 250 mv / -240 mv > 680 k 2.5 v 720 mv
l6585de ballast section 23/33 figure 12. end-of-life protection in lamp-to-ground configuration
ballast section l6585de 24/33 figure 13. end-of-life protection in bl ocking capacitor-to-ground configuration
l6585de ballast section 25/33 6.6 over-current protection the appearance of over-current and hard switching events are related to a symmetrical increase of the ohmic resistance of the two cathodes. the overall effect results in an increased equivalent resistance of the la mp and a subsequent modification of the resonance curve of the resonance network (see figure 14 ). figure 14. resonance curve modification due to lamp ageing the increasing of the resonant peak causes over-current that is managed by the l6585de in the same way as in ignition mode, but the limiting threshold and checking threshold are respectively 1.05 v and 0.82 v. 6.7 hard switching protection when f run is equal to the peak of the resonance curve, the load seen by the half-bridge is purely resistive. in this case, zero voltage switching is no longer present and the mosfet experiences high current spikes at turn on. the voltage at hbcs pin shows these peaks whose voltage value can be greater than 3 v with a duration that depends on how close the resonant frequency and the operating frequency are. typical values go from 40 ns to around 200 ns. these spikes may overheat the mosfets but, if correctly detected, can prevent the risk of working below the resonance frequency (capacitive mode). the l6585de can detect these spikes by means of a 2.75 v threshold on hbcs pin, and a counter that shuts down the ic if 350 (typ.) subsequent spikes are detected. this protection is blanked both during preheating and ignition. 6.8 choke saturation protection ballast choke saturation implies that very high currents flow into resonance network and an almost instant modification of the resonance cu rve occurs in a way that the operating point lies immediately in capacitive mode. steady operation in capacitive mode heavily damages the ballast. old lam p new lam p frun
ballast section l6585de 26/33 figure 15. example of capacitive mode operation due to ballast choke saturation therefore, in ignition and run mode a comparator, connected to the hbcs pin, is active with a threshold respectively equal to 2.75 v and 1.6 v. it senses very high currents flowing in the ballast sense resistor and immediately latche s the ic in low consumption mode. the width of the triggering spike is above 200 ns. this guarantees that, during run mode, hard switching events (typical duration between 40 ns and 100 ns) cannot trigger the comparator. however, hard switching protection and an ti-saturation protection are not perfectly independent. regarding the pulse width we can indicate four different regions: a) spikes with a duration less than 40 ns: (noise region) no protection can be triggered. b) spikes with a duration between 40 ns and 100 ns: (hsw region) only hard switching protection will be ac tivated after ar ound 420 events. c) spikes with a duration between 100 ns and 200 ns: (uncertainty region) hard switching protection is activated, but also anti-saturation protection can be activated, which may result in a sort of ea rly activation of hard switching protection or retarded activation of anti-saturation prot ection (in this case the saturation of the choke won?t be deep). d) spikes with a duration longer than 200 ns: (asp region) anti-s aturation pr otection will certainly be activated at the first event. hbcs out pin good working saturating slightly capacitive mode
l6585de ballast section 27/33 figure 16. half-bridge current sense pulse detection areas
ballast section l6585de 28/33 table 6. table of faults fault active during condition ic behavior required action ph ign run fault with immediate activation of latched operating mode shutdown v ctr < 0.75 v - drivers stopped - ic low consumption (vcc clamped) v ctr > 0.75 v (ic restarts with ph sequence) pfc feedback disconnection v ctr > 3.4 v and v inv < 1.2 v - drivers stopped - ic low consumption (vcc clamped) board failure half bridge anti- saturation protection ignition: v hbcs > 2.75 v - drivers stopped - ic low consumption vcc clamped) turn off ? turn on sequence run mode: v hbcs > 1.6 v fault with immediate activation of a non latched operating mode pfc dynamic over-voltage v ctr > 3.4 v - pfc driver stopped wait for output voltage reduction pfc protection over-current v pfccs > 1.7 v - pfc driver stopped wait for next starter event fault with timed activation of latched operating mode pfc static ovp v comp < 2.25 v - pfc driver stopped - tch cycle starts - at the end of cycle, if v comp < 2.25 v ic is latched check the mains voltage lamp end-of-life v eol outside allowed range (set by r eolp ) - tch cycle starts - at the end of the cycle if v eol is out of range the ic is latched replace the lamp with a new one lamp over-current ignition: v hbcs > 1.6 v - frequency control activated and reduced tch cycle (rtc) starts - at the end of rtc the threshold is reduced (1.05 v during ignition and 0.82 v during run mode) - if v hbcs >reduced threshold ic is stopped replace the lamp with a new one run mode: v hbcs > 1.05 v lamp ageing causing hard switching v hbcs > 2.75 v - after 350 subsequent hard switching events ic is stopped replace the lamp with a new one 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9
l6585de package mechanical data 29/33 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark.
package mechanical data l6585de 30/33 figure 17. package dimensions table 7. so-20 mechanical data dim. mm. inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 12.60 13.00 0.496 0.512 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 m 0.75 0.029 s 8 (max.)
l6585de ordering information 31/33 8 ordering information table 8. order codes order codes package packaging l6585de so-20 tube L6585DETR so-20 tape and reel
revision history l6585de 32/33 9 revision history table 9. document revision history date revision changes 27-nov-2008 1 initial release 10-apr-2009 2 updated ta b l e 1 , ta b l e 2 , ta b l e 3 , figure 4
l6585de 33/33 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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